The present invention relates to a flash memory device and programming method thereof and, more particularly, to a flash memory device and programming method thereof, in which a verify operation can be executed during a program operation.
In recent years, there has been an increasing demand for semiconductor memory devices which can be electrically programmed and erased without a refresh function of rewriting data at regular intervals. Active research has also been conducted to develop high integration memory devices and large-capacity memory devices that can store a large amount of data.
For a high integration memory cell, a NAND type flash memory device has been developed in which a plurality of memory cells are connected in series to constitute a string. The NAND type flash memory device is programmed or erased by injecting or draining electrons into or out of the floating gate of the NAND type flash memory device by the Fowler-Nordheim Tunneling method.
The NAND type flash memory device employs a page buffer to store a large capacity of information in short bursts and to verify whether data has been normally programmed or erased. The page buffer generally includes a single register for temporarily storing data. Recently, the page buffer has been expanded to include a dual register to increase data program speed.
FIG. 1 is a block diagram of a page buffer having a dual register structure of a general NAND type flash memory device. A program operation and a copyback operation are performed using a main register 24 and a cache register 25, respectively. The main register 24 is used to execute read and program erase verify operations. An operation of the page buffer upon program verification is described below.
If discharge signals DISCHe, DISCHo are applied to a verify signal supply unit 21, a verify signal VIRPWR, which maintains a voltage level of 0V, is applied to one of even and odd bit lines BLe, BLo. The main register 24 includes a latch 27. An output node of the latch 27 is reset in response to a reset signal. If a precharge signal of a low level is applied to a precharge unit 23, a power supply voltage Vcc is supplied to a sense node SO, which maintains a high level. Thereafter, an even bit line select signal BSLe having a voltage level of a first voltage V1 is applied to a bit line select unit 22 and, therefore, the even bit line BLe is precharged to V1-Vt. The bit line select unit 22 is then applied with the even bit line select signal BSLe of a low level to evaluate the cell. The precharge signal of a high level is applied to the precharge unit 23, so that the node that supplies the sense node SO with the power supply voltage Vcc is blocked. Hence, the bit line select unit 22 is applied with the even bit line select signal BSLe having a voltage level of a second voltage V2. Thereafter, the main register 24 is applied with a read signal and, therefore, the voltage levels of the input and output nodes of the latch 27 are changed according to the voltage level of the sense node SO, which is changed according to the programmed or erased state of the cell. That is, in the case of a programmed cell, the sense node SO maintains a high voltage level, and in the case of the erased cell, the sense node SO is discharged to a low voltage level. When the sense node SO maintains a high voltage level, the voltage level of the input node of the sense node SO becomes a low level and the output node thereof becomes a high level. A detection signal terminal floats due to the high voltage level of the output node. Meanwhile, when the sense node SO maintains a low voltage level, the voltage levels of the input node and the output node of the sense node SO are not changed, so the output node maintains a low voltage level. The voltage level of the detection signal becomes a high level due to the low voltage level of the output node. Accordingly, in the case of a programmed cell, the voltage level of the detection signal floats, and in the case of an erased cell, the voltage level of the detection signal becomes a high level.
One page buffer, constructed as described above, is coupled to each bit line pair (i.e., an even bit line and an odd bit line) of a flash memory device. Further, as shown in FIG. 2, detect signal nodes nWDO_L of each page buffer are bound to one line and output. In other words, in the case of a flash memory device comprised of 512 bit lines, 512 detect signal nodes nWDO_L from 512 page buffers are integrated into one line and output. Thus, since a 1-bit detection signal nWDO is output on a 512-page-buffer basis, pass or fail bits are produced using a 16-bit detection signal nWDO.
The conventional verify method of the flash memory device can check only a pass or fail state, but cannot check how many fail bits have occurred.